Generally, a path for transferring or receiving information could be referred to as a channel. Information may be transmitted within the channel through wired or wireless communication way. Furthermore, a channel may be referred to as storing information in a semiconductor memory device and reading the stored information from the semiconductor memory device. The channel may be a physical path for storing information in the semiconductor memory device and reading the stored information form the semiconductor memory device.
When information is transmitted through the channel, the transmitted information may be corrupted and may include a number of errors. If the number of errors in transmitted information exceeds predetermined number of errors, a decoder may not be able to restore the initial transmission.
Please reference to U.S. Pat. No. 8,171,382 B2. Depending on the channel (memory channel) response to transmitted information, the error rate in the channel may be relative large, especially the channel is a multi-bit memory device. In order to eliminate error induced from channel, an easy way is to prevent data stream transmitted on channel has long sequence of logical ‘0’ or ‘1’. A scrambler is designed to prevent such long sequence of logical ‘0’ or ‘1’, and a descrambler is to reconstruct original signal sequence. Conventionally the scrambler is implemented as a binary linear feedback shift register (LFSR), and the descrambler is implemented as a binary linear feed forward shift register.
Please refer to FIG. 1, which shows a conventional storage device system. A storage device 14 is electrically connected with a HOST interface 11, a RAM 12, an ECC engine 13, a scramble engine 15, and a processor 16. For case of data saving to storage device 14, data may come from the HOST interface 11. The processor 16 may calculate a physical address to be saved to the storage device 14, and pass data stream to the ECC engine 13 for encoding. The ECC engine 13 for encoding may be used X1 bits to protect X2 bits of information data. That is, the X1 is larger, and the performance of protection is better. That is, every X2 bits data transfers on the bus, the ECC engine 13 for encoding may generate a set of X1 bits error correction code appended at the end of information data. The engine 15 may include a scrambler 151 and a descrambler 152. The scrambler 151 may be a LFSR (linear feedback shift register) scrambler to take these data and output a scrambled data sequence to the storage device 14. For case of data reading from the storage device 14, the processor 16 may calculate the physical address of a desired data, and read it out to the descrambler 152. Then, the descrambler 152 may be a LFSR descrambler to receive the data from the storage device 14, and output the descrambled data. The ECC decoding engine 13 may check the error correction code every X2 bits, and try to recover the errors. The recovered data may be sent to the HOST interface 11.
Currently, research efforts are continuing in the area of detecting error from corrupted information, and eliminating the corrupted information from the initial transmission. Encoding error control codes may be referred to as a process of adding error control codes to initial information prior to transmitting. Decoding error control codes may be referred to as a process of separating error control code from received transmission information to restore the initial information.